The present invention relates to a method of shallow trench isolation for a semiconductor device; and, more particularly, to a method of filling a trench for isolation in a semiconductor device.
An integrated circuit is formed from a silicon substrate within and upon whose surfaces are formed resistors, transistors, diodes and other electrical circuit elements. The electrical circuit elements are connected internally and externally to the silicon substrate upon which they are formed through patterned conductor layers that are separated by dielectric layers.
As integrated circuit device technology has advanced and integrated circuit device dimensions have decreased, it has become increasingly common within advanced integrated circuits to employ a trench isolation method such as a shallow trench isolation (STI) method and a recessed silicon dioxide isolation (ROI) method to form trench isolation regions nominally coplanar with adjoining active semiconductor regions of a silicon substrate. Such a trench isolation method typically employs a chemical mechanical polish (CMP) planarizing method to provide a nominally planarized surface to a trench isolation region formed from a trench fill dielectric layer formed within the trench.
To fill a STI trench, an isolation dielectric such as silicon dioxide is deposited over a silicon substrate by using chemical vapor deposition (CVD) technique, such as low pressure TEOS (tetraethylorthosilicate) (LPCVD), TEOS-ozone atmospheric pressure (APCVD), sub-atmospheric pressure (SACVD), or high density plasma CVD (HDP-CVD). In particular, a TEOS-ozone (O3-TEOS) oxide film is widely used as the isolation dielectric for filling the STI trench because of a superior surface mobility thereof.
A prior art associated with the shallow trench isolation (STI) and the integration of trench filling by TEOS-ozone will be explained with reference to FIGS. 1 and 2.
A silicon substrate 10 is shown in FIG. 1; formed on the silicon substrate 10 is a sacrificial layer 12, which includes a layer of pad thermal silicon dioxide (not shown) grown on a surface of the silicon substrate 10 and a layer of pad silicon nitride (not shown) deposited on the layer of pad thermal silicon dioxide. A trench 14 is etched through the sacrificial layer 12 and partially into the substrate 10, followed by thermal silicon dioxide 16 growth inside the trench 14, i.e., sidewalls and a bottom thereof. A reactive ion etch (RIE) process and a LPCVD process are usually used for forming the trench 14 and the silicon dioxide 16, respectively.
Then, in FIG. 2, a TEOS-ozone oxide film 18 is deposited over the silicon substrate 10 to fill the trench 14 by using APCVD, followed by annealing. Finally, the TEOS-oxide film 18 is planarized by using CMP.
There are some process problems in the prior art associated with shallow trench isolation (STI) and the integration of trench filling by TEOS-ozone. Process problems that arise under certain conditions are the formation of voids and seams in the isolating dielectric, i.e., the TEOS-ozone oxide, which fills the trench. Since the formation of voids or seams more frequently occurs at a higher aspect ratio of the trench, the prior art STI cannot be employed for a highly integrated semiconductor device that may require a high aspect ratio trench for a decreased device dimension. Accordingly, a more improved gap fill method has been developed to avoid the occurrence of the voids or seams in the TEOS-ozone oxide.
It is, therefore, an object of the present invention to provide an improved method of filling a high aspect ratio trench for shallow trench isolation.
In accordance with a preferred embodiment of the invention, there is provided a method of shallow trench isolation, including the steps of: forming a trench into a substrate; forming a polysilicon layer on sidewalls and a bottom of the trench; thermally oxidizing the polysilicon layer so as to form a thermal oxide layer on the polysilicon layer; removing a portion of the thermal oxide layer such that the polysilicon layer is exposed on the bottom of the trench, while leaving the thermal oxide layer on the sidewalls of the trench; and depositing a TEOS-ozone oxide layer on the substrate to fill the trench.
In accordance with another preferred embodiment of the present invention, there is provided a shallow trench isolation method, including the steps of: forming a sacrificial layer on a silicon substrate; forming a trench through the sacrificial layer and partially into the silicon substrate; thermally oxidizing exposed portions of the silicon substrate in the trench such that a thermal oxide layer is formed on sidewalls and a bottom of the trench; removing a portion of the thermal oxide layer on the bottom of the trench, while leaving the thermal oxide layer on the sidewalls of the trench; and depositing a TEOS-ozone oxide layer on the silicon substrate to fill the trench.